Photos are available in the DATE 2024 Gallery.

The time zone for all times mentioned at the DATE website is CET – Central Europe Time (UTC+1). AoE = Anywhere on Earth.

Registration & Participation

The online registration to the conference is only possible via the online registration platform until 27 March 2024. Please kindly note that everyone who wants to attend the conference or single sessions, must create an account and register. If you create an account, you can for instance check your registration or make additional programme bookings later.

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DATE 2024 Awards

EDAA Achievement Award 2024

Ingrid Verbauwhede, KU Leuven, BE

https://www.date-conference.com/edaa-achievement-award-2024-goes-ingrid-verbauwhede

IEEE CEDA Service Award

Ian O’Connor, École Centrale de Lyon, FR

IEEE CS TTTC Outstanding Contribution Award

Andy D. Pimentel, University of Amsterdam, NL

ACM SIGDA/CEDA/EDAA PhD Forum Prize

Lukas Burgholzer, TU Munich, DE

DESIGN AUTOMATION TOOLS AND SOFTWARE FOR QUANTUM COMPUTING

Matteo Risso, Politecnico di Torino, IT

AUTOMATIC HARDWARE-AWARE DESIGN AND OPTIMIZATION OF DEEP LEARNING MODELS

EDAA Outstanding Dissertation Awards

Topic 1 – New directions in systems design methods and tools, simulation and validation, embedded software design and optimization for embedded, cyber-physical, secure and learning systems

Stefan Nikolic, EPFL, CH (Advisor: Prof. Paolo Ienne, EPFL, CH)

Automating the Design of Programmable Interconnect for Reconfigurable Architectures -

Topic 2 – New directions in SoC platforms co-design, novel architectures for future computing in design flows, and power management

NO AWARD

Topic 3 – New directions in logic, physical design and CAD for analog/mixed-signal, nano-scale and emerging technologies

Nan Wu, UC Santa Barbara, US (Advisor: Prof. Yuan Xie, UC Santa Barbara, US)

Machine Learning Empowered Agile Hardware Design and Design Automation

Topic 4 – New directions in safety, reliability and security-aware hardware design, validation and test

Zhixin Pin, University of Florida, US (Advisor: Prof. Prabhat Mishra, University of Florida, US)

Defending Systems Against Malicious Attacks using Machine Learning

DATE Fellow Award

Ian O´Connor, École Centrale de Lyon, FR

For outstanding service contribution for DATE as General Chair of DATE 2023.

DATE Best Paper Awards

D-Track:

Xueyuan Liu1, Zhuoran Song1, Guohao Dai1, Gang Li1, Can Xiao2, Yan Xiang2, Dehui Kong2, Ke Xu2 and Xiaoyao Liang1

1Shanghai Jiao Tong University, CN; 2Sanechips Technology, CN



FusionArch: A Fusion-Based Accelerator for Point-Based Point Cloud Neural Networks (Session BPA04 Novel Architecture Solutions)

A-Track:

Matteo Risso1, Chen Xie1, Francesco Daghero1, Alessio Burrello2, Seyedmorteza Mollaei1, Marco Castellano3, Enrico Macii1, Massimo Poncino1 and Daniele Jahier Pagliari1

1Politecnico di Torino, IT; 2Politecnico di Torino | Università di Bologna, IT; 3STMicroelectronics, IT



HW-SW Optimization of DNNs for Privacy-preserving People Counting on Low-resolution Infrared Arrays (Session BPA01 Better Machine Learning)

T-Track:

Yujin Lim, Dongwhee Kim and Jungrae Kim, Sungkyunkwan University, KR



SELCC: Enhancing MLC Reliability and Endurance with Single-Cell Error Correction Codes (Session BPA02 Reliability and Optimizations)

E-Track:

Yifeng Xiao1, Chanwook Oh1, Michele Lora2 and Pierluigi Nuzzo1

1University of Southern California, US; 2Università di Verona, IT



Efficient Exploration of Cyber-Physical System Architectures Using Contracts and Subgraph Isomorphism (Session BPA04 Novel Architecture Solutions)

Outstanding Reviewer Awards

for contributing most valuable reviews for submitted papers, by giving insightful and constructive feedback to the authors, timely submitting manuscript reviews as well as consistent and timely engagement through the selection process, including both online discussion and TPC meeting.

D-Track:

Todor Stefanov, Leiden University, NL

Alejandro Valero, Universidad de Zaragoza, ES

A-Track:

Michael Pehl, Technical University of Munich, DE

Giovanni Amedeo Cirillo, STMicroelectronics, IT

T-Track:

Harish Dixit, Meta Platforms Inc., US

Riccardo Cantoro, Politecnico di Torino, IT

E-Track:

Hadjer Benmeziane, IBM Research, CH

Mohammad Ashjaei, Mälardalen University, SE

Young People Programme University Fair Award

Marc Solé Bonet1, Ivan Rodriguez Ferrandez2, Dimitris Aspetakis1, Jannis Wolf1, Matina Maria Trompouki1and Leonidas Kosmidis2

1BSC, ES; 2UPC | BSC, ES



Hardware and Software Designs for High Performance and Reliable Space Processing

 

We would like to thank the jury who carefully reviewed all presentations and selected the winner.

Hassan Najafi, Antonio Miele, Marcello Traiola, Angeliki Kritikakou, Jose Cano Reyes, Li Zhang

ASD Outstanding Paper Award

in line with the DATE Special Initiative "Autonomous Systems Design"

Justin Davis and Mehmet Belviranli, Colorado School of Mines, US



Context-aware Multi-Model Object Detection for Diversely Heterogeneous Compute Systems

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Download DATE 2024 Proceedings

Download of DATE 2024 Proceedings is possible below after login.

You have been informed about your login credentials after your registration for the conference.

If you can't see the download link below after successful login, please check the registration desk or contact

Anja Schröter, K.I.T. Group GmbH Dresden, DEConference Organisation | Registration
Anja Schröter, K.I.T. Group GmbH Dresden, DE
date-registration@kitdresden.de

EDAA Achievement Award 2024 goes to Ingrid Verbauwhede

Ingrid VerbauwhedeThe Achievement Award is given to individuals who made outstanding contributions to state of the art in electronic design, automation and testing of electronic systems in their life. To be eligible, candidates must have made innovative contributions that impacted how electronic systems are being designed.

Past recipients have been Kurt ANTREICH (2003), Hugo DE MAN (2004), Jochen JESS (2005), Robert BRAYTON (2006), Tom W. WILLIAMS (2007), Ernest S. KUH (2008), Jan M. RABAEY (2009), Daniel D. GAJSKI (2010), Melvin A. BREUER (2011), Alberto L. SANGIOVANNI-VINCENTELLI (2012), Peter MARWEDEL (2013), Rolf ERNST (2014), Lothar THIELE (2015), Giovanni DE MICHELI (2016), C. L. David LIU (2017), Mary Jane IRWIN (2018), Jacob ABRAHAM (2019), Luca BENINI (2020), Georges GIELEN (2021), Edward A. LEE (2022), and Jason Cong (2023).

Dr. Ingrid Verbauwhede is currently a full professor in the research group COSIC at KU Leuven and an adjunct professor at UCLA. She is recognized as a pioneer in hardware security. She is an expert in interdisciplinary research linking design for security with novel technologies and circuits as well as in investigating the requirements of novel cryptographic algorithms on secure hardware and HW/SW co-design. Her ability to cross the gap between cryptographic algorithm and protocol development, and actual implementation in hardware, software, and embedded systems has been widely recognized. In fact, she has made outstanding contributions, resulting in highly cited work, in several key aspects of EDA: electronic design for security, design automation and integration of security in digital EDA design flows, and test for security, with a focus on attacks and countermeasures to resist side-channel and fault attacks. Her work's application covers ASICs, FPGAs, and embedded microcontrollers. She has more than 450 publications in international journals and conferences and, according to Google Scholar, she has more than 30000 citations and an overall H-index of 90.

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Authors' Guidelines for Audio-Visual Presentation

This document describes the guidelines to prepare and present audio-visual materials at DATE 2024. Please read all instructions carefully and follow them strictly to maintain the highest possible standards. Even experienced speakers should read the following paragraphs, as they cover several problems that have arisen over the years.

DATE provides a centralised presentation management system for speakers of D, A, T and E Track sessions, Late Breaking Results paper presentations, Multi-Partner Project presentations, Focus Sessions, Special Day and Special Initiative ASD presentations as well as presentations in line with the Young People Programme. It will not be possible to use own devices for presentations in the session rooms.

The centralised presentation management will not be provided for workshops (incl. Special Initiative ASD workshop) and embedded tutorials. Workshop and embedded tutorial speakers will receive presentation information from the workshop/embedded tutorial organisers.

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Keynotes

OK01.1 Opening Keynote: CHIPLET STANDARDS: A NEW ROUTE TO ARM-BASED CUSTOM SILICON

Start
Robert Dimon

Robert Dimond, ARM, United Kingdom

Abstract

A key challenge our partners are consistently looking to solve is: How can we continue to push performance boundaries, with maximum efficiency, while managing costs associated with manufacturing and yield? Today, as the ever more complex AI-accelerated computing landscape evolves, a key solution emerging is chiplets. Chiplets are designed to be combined to create larger and more complex systems that can be packaged and sold as a single solution, made of a number of smaller dice instead of one single larger monolithic die. This creates interesting new design possibilities, with one of the most exciting being a potential route to custom silicon for manufacturers who historically chose off-the-shelf solutions. This talk will describe two complementary approaches to realising this chiplet opportunity: · Decomposing an existing system across multiple chiplets, in the same way a monolithic chip is composed of IP blocks. · Aggregating well-defined peripherals across a motherboard into a single package. Both of these approaches require collaboration in standards to align on the many non-differentiating choices in chiplet partitioning. This talk will describe the standards framework that Arm is building with our partners, and the broader industry. Including, own specifications such as the Arm Chiplet System Architecture (Arm CSA), AMBA chip-to-chip and the role of industry standards such as UCIe.

OK02.1 Opening Keynote: ENLIGHTEN YOUR DESIGNS WITH PHOTONIC INTEGRATED CIRCUITS

Start
Luc Augustin

Luc Augustin, SMART Photonics, Netherlands

Abstract

The field of integrated photonics holds great promise for overcoming societal challenges in data and telecom, autonomous driving and healthcare in terms of cost, performance, and scalability. Similar to the semiconductor industry, the ever-increasing demands of various applications are driving the necessity for platform integration in photonics as well, enabling seamless integration of diverse functionalities into compact and efficient photonic devices. This high level of integration reduces footprint and drives down system level costs. In this trend towards high levels of integration , Indium Phosphide (InP) is the material of choice for long-distance communication lasers, owing to its proven track record over several decades. Leveraging standardized fabrication processes, the cost and performance targets can be addressed. The key advantages of InP-based integration lie in its ability to fully integrate lasers, amplifiers, modulators, and passives, providing a flexible and reliable platform for building complex Photonic Integrated Circuits (PICs). This paper will address the photonic integration platforms, the applicability to current and future markets requiring the need for further heterogenous integration with other technologies, and the change to a foundry business model, much like its electronics counterpart.

LK01.1 IEEE CEDA Distinguished Lecturer Lunchtime Keynote: AI MODELS FOR EDGE COMPUTING: HARDWARE-AWARE OPTIMIZATIONS FOR EFFICIENCY

Start

Hai (Helen) Li, Duke University, United States

Hai (Helen) Li
Abstract

As artificial intelligence (AI) transforms various industries, state-of-the-art models have exploded in size and capability. The growth in AI model complexity is rapidly outstripping hardware evolution, making the deployment of these models on edge devices remain challenging. To enable advanced AI locally, models must be optimized for fitting into the hardware constraints. In this presentation, we will first discuss how computing hardware designs impact the effectiveness of commonly used AI model optimizations for efficiency, including techniques like quantization and pruning. Additionally, we will present several methods, such as hardware-aware quantization and structured pruning, to demonstrate the significance of software/hardware co-design. We will also demonstrate how these methods can be understood via a straightforward theoretical framework, facilitating their seamless integration in practical applications and their straightforward extension to distributed edge computing. At the conclusion of our presentation, we will share our insights and vision for achieving efficient and robust AI at the edge.

ASD05K.1 ASD Embedded Keyote: Certainty or Intelligence: Pick One!

Start

Edward Lee, University of California, Berkeley, United States

Edward Lee
Abstract

Mathematical models can yield certainty, as can probabilistic models where the probabilities degenerate. The field of formal methods emphasizes developing such certainty about engineering designs. In safety critical systems, such certainty is highly valued and, in some cases, even required by regulatory bodies. But achieving reasonable performance for sufficiently complex environments appears to require the use of AI technologies, which resist such certainty. This extended abstract suggests that certainty and intelligence may be fundamentally incompatible.

LK02.1 Special Day Lunchtime Keynote: DATA CENTER DEMAND RESPONSE FOR SUSTAINABLE COMPUTING: MYTH OR OPPORTUNITY?

Start

Ayse Coskun, Boston University, United States

Ayse Coskun
Abstract

In our computing-driven era, the escalating power consumption of modern data centers, currently constituting approximately 3% of global energy use, is a burgeoning concern. With the anticipated surge in usage accompanying widespread adoption of AI technologies, addressing this issue becomes imperative. This keynote discusses a potential solution: integrating data centers into grid programs such as “demand response”. This strategy not only augments power usage without necessitating new fossil-fuel infrastructure, but also facilitates more ambitious renewable deployment. However, the unique scale, operational constraints, and future projections of data centers present distinct and urgent challenges for implementing demand response. On the other hand, data centers, in contrast to other electricity consumers, boast greater flexibility in power control and offer the potential for collaborative optimization. This intersection of challenges and capabilities opens avenues for designing intelligent solutions that dynamically adjust data center power usage in response to grid requirements while meeting performance demands.

This keynote delves into the opportunities as well as the myths inherent in this perspective on improving data center sustainability. While obstacles such as creating requisite software infrastructure, establishing institutional trust, and addressing privacy concerns are prominent, the landscape is evolving. Noteworthy achievements have emerged in the development of intelligent solutions that can be swiftly implemented in data centers to accelerate demand response. These multifaceted solutions encompass dynamic power capping, load scheduling, load forecasting, market bidding, and collaborative optimization. This keynote offers insights into the exciting journey towards making sustainable computing a reality.

LK03.1 VALIDATION AND VERIFICATION OF AI-ENABLED VEHICLES IN THEORY AND PRACTICE

Start
Marilyn Wolf & William Widen
Abstract

- Unfortunately, the initial keynote presentation "RESPONSIBLE ARTIFICIAL INTELLIGENCE SYSTEMS: FROM TRUSTWORTHINESS TO GOVERNANCE" by Francisco Herrera (University of Granada, ES) cannot take place as planned and will be substituted by Marilyn Wolf1 and William Widen2 (1University of Nebraska, US; 2University of Nebraska – Lincoln, US):

This talk will consider engineering methods for the evaluation of the safety of AI-enabled vehicles. We do not yet have theories and models for AI systems equivalent to those used to guide software/hardware verification and manufacturing test. However, engineers can adapt existing methods to help provide some assurance as to the safety and effectiveness of AI-enabled vehicles. We will also consider the role of management in the monitoring of validation for AI-enabled vehicles.

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